1. Technical Field
The present disclosure relates to a receiving apparatus and a demodulation method for receiving and demodulating a frequency shift keying (FSK) modulated signal.
2. Description of the Related Art
As one of the modulation methods for digital communication, a frequency shift keying (FSK) modulation method is known where the values of digital signals, “0” and “1”, are assigned to different frequencies, with which digital signals are modulated. An example of a demodulation method for FSK modulated signals is described in Japanese Unexamined Patent Application Publication No. 9-130300.
FIG. 7 is a block diagram illustrating a receiving apparatus (specifically, a multi-frequency shift keying demodulator) described in Japanese Unexamined Patent Application Publication No. 9-130300. The receiving apparatus in FIG. 7 includes an antenna 1, a first demodulator 2 employing a frequency hopping spread spectrum method, and a second demodulator (MFSK demodulator) 3 employing a MFSK method. The first demodulator 2 includes a mixer 5, a frequency synthesizer 6, and a hopping pattern generator 7. The second demodulator 3 includes a band pass filter (BPF) 8, an analog-to-digital (AD) converter 9, a fast Fourier transformer (FFT) 10, a maximum value selector 11, and a decoder circuit 12.
The mixer 5 generates a first decode signal by synchronizing and mixing a spread spectrum signal which is received by the antenna 1 and amplified by an amplifier (not illustrated) with a hopping local signal provided by the frequency synthesizer 6 and by performing an inverse spread spectrum process on the spread spectrum signal. The BPF 8 removes an unnecessary signal from the first decode signal output from the mixer 5. The AD converter 9 converts the first decode signal output from the BPF 8, which is an analog signal, into a digital signal.
The FFT 10 truncates the digital signal output from the AD converter 9 by a predetermined time window and performs fast Fourier transform to simultaneously detect a plurality of frequency components (FFT signals) in the digital signal.
The maximum value selector 11 detects a change in a frequency component representing plural maximum amplitude values in the FFT signal output from the FFT 10 and generates a code word data signal S1 having plural code word chips as a received signal, according to the change in the frequency component. Further, the maximum value selector 11 performs maximum likelihood detection between the code word data signal S1 and a plurality of code word pattern data signals S2 that are set in advance in accordance with bit patterns of the second demodulation data, and thereby selects the code word pattern data signal S2 which has the highest matching degree with the code word data signal S1.
The decoder circuit 12 decodes the code word pattern data signal S2 selected by the maximum value selector 11 into a digital signal having the predetermined number of bits, and outputs the signal as the second demodulation data signal (demodulation data).
As described above, in the multi-frequency shift keying demodulator according to Japanese Unexamined Patent Application Publication No. 9-130300, fast Fourier transform is performed on the FSK modulated signal to detect a plurality of frequency components included in the modulated signal, and a data signal is obtained using the plural frequency components. The technique described in Japanese Unexamined Patent Application Publication No. 9-130300 does not use an envelope detector or require a plurality of band pass filters. Therefore, demodulation can be performed accurately at a high speed without variations in characteristics.
However, in the above conventional technique, Fourier transform calculation is performed for each frequency component; therefore, a large amount of calculation is performed, resulting in an increase in circuit size and power consumption. In addition, in multi-rate communication where a system is able to set a plurality of transmission rates having different bandwidths, the above conventional technique causes a significant increase in circuit size and power consumption, because the number of demodulation processing blocks would need to be the same as the number of transmission rates in order to perform a receiving process to simultaneously receive data at a plurality of transmission rates.